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| author | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 10:47:31 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-02-05 10:47:31 -0800 |
| commit | b6a1f627b5871e750fe6a559fbb42334c7de8b84 (patch) | |
| tree | f1b284aebe30d0f7eabd9e8919b4275a38ff2ae4 /tests/techmap | |
| parent | 5aaa19f1ab33394accbe633cd96a3fbe281dd09a (diff) | |
| parent | 5ebdc0f8e07989b79337ced0553bd28819a8cf3e (diff) | |
| download | yosys-b6a1f627b5871e750fe6a559fbb42334c7de8b84.tar.gz yosys-b6a1f627b5871e750fe6a559fbb42334c7de8b84.tar.bz2 yosys-b6a1f627b5871e750fe6a559fbb42334c7de8b84.zip | |
Merge remote-tracking branch 'origin/master' into eddie/shiftx2mux
Diffstat (limited to 'tests/techmap')
| -rw-r--r-- | tests/techmap/abc9.ys | 29 |
1 files changed, 29 insertions, 0 deletions
diff --git a/tests/techmap/abc9.ys b/tests/techmap/abc9.ys index 62b5dfef6..2140dde26 100644 --- a/tests/techmap/abc9.ys +++ b/tests/techmap/abc9.ys @@ -39,6 +39,35 @@ design -load gold scratchpad -copy abc9.script.flow3 abc9.script abc9 -lut 4 +design -reset +read_verilog <<EOT +module top(input a, b, output o); +(* keep *) wire w = a & b; +assign o = ~w; +endmodule +EOT + +simplemap +equiv_opt -assert abc9 -lut 4 +design -load postopt +select -assert-count 2 t:$lut + + +design -reset +read_verilog -icells <<EOT +module top(input a, b, output o); +wire w; +(* keep *) $_AND_ gate (.Y(w), .A(a), .B(b)); +assign o = ~w; +endmodule +EOT + +simplemap +equiv_opt -assert abc9 -lut 4 +design -load postopt +select -assert-count 1 t:$lut +select -assert-count 1 t:$_AND_ + design -reset read_verilog -icells <<EOT |