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authorMarcelina Koƛcielnicka <mwk@0x04.net>2021-02-23 21:23:26 +0100
committerMarcelina Koƛcielnicka <mwk@0x04.net>2021-02-24 01:07:34 +0100
commitb05b98521c781fef0f9d900a53310cad9e1434b0 (patch)
treeb63a6620dc887d662ee1c7340937e2e96233e420 /tests/techmap
parentcde73428b046a1a87339f8a069f59ce732794617 (diff)
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Add tests for some common techmap files.
Diffstat (limited to 'tests/techmap')
-rw-r--r--tests/techmap/adff2dff.ys19
-rw-r--r--tests/techmap/dff2ff.ys16
-rw-r--r--tests/techmap/pmux2mux.ys15
3 files changed, 50 insertions, 0 deletions
diff --git a/tests/techmap/adff2dff.ys b/tests/techmap/adff2dff.ys
new file mode 100644
index 000000000..53f7d2f08
--- /dev/null
+++ b/tests/techmap/adff2dff.ys
@@ -0,0 +1,19 @@
+read_verilog -icells << EOT
+module top(...);
+
+input [1:0] D;
+input C, R;
+output [1:0] Q;
+
+always @(posedge C, posedge R)
+ if (R)
+ Q <= 0;
+ else
+ Q <= D;
+
+endmodule
+EOT
+
+proc
+
+equiv_opt -async2sync techmap -map +/adff2dff.v
diff --git a/tests/techmap/dff2ff.ys b/tests/techmap/dff2ff.ys
new file mode 100644
index 000000000..5adf14b07
--- /dev/null
+++ b/tests/techmap/dff2ff.ys
@@ -0,0 +1,16 @@
+read_verilog -icells << EOT
+module top(...);
+
+input [1:0] D;
+input C;
+output [1:0] Q;
+
+always @(posedge C)
+ Q <= D;
+
+endmodule
+EOT
+
+proc
+
+equiv_opt techmap -map +/dff2ff.v
diff --git a/tests/techmap/pmux2mux.ys b/tests/techmap/pmux2mux.ys
new file mode 100644
index 000000000..1714a6b87
--- /dev/null
+++ b/tests/techmap/pmux2mux.ys
@@ -0,0 +1,15 @@
+read_verilog -icells << EOT
+module top(...);
+
+input [3:0] A;
+input [3:0] B0;
+input [3:0] B1;
+input [1:0] S;
+output [3:0] O;
+
+\$pmux #(.WIDTH(4), .S_WIDTH(2)) pm (.A(A), .B({B1, B0}), .S(S), .Y(O));
+
+endmodule
+EOT
+
+equiv_opt techmap -map +/pmux2mux.v