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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-07-21 16:41:26 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-08-07 13:21:34 +0200 |
commit | 5693386a4ec7fc05c12a6c98900e19d5b2851396 (patch) | |
tree | ce94d0b34fed69f30ccc8694a285bc6adf9cd289 /tests/techmap | |
parent | a0e99a9f3f0a52e3a6f2000791d93b54ce116928 (diff) | |
download | yosys-5693386a4ec7fc05c12a6c98900e19d5b2851396.tar.gz yosys-5693386a4ec7fc05c12a6c98900e19d5b2851396.tar.bz2 yosys-5693386a4ec7fc05c12a6c98900e19d5b2851396.zip |
Remove now-redundant dff2dffs pass.
Diffstat (limited to 'tests/techmap')
-rw-r--r-- | tests/techmap/dff2dffs.ys | 50 |
1 files changed, 0 insertions, 50 deletions
diff --git a/tests/techmap/dff2dffs.ys b/tests/techmap/dff2dffs.ys deleted file mode 100644 index 105a89400..000000000 --- a/tests/techmap/dff2dffs.ys +++ /dev/null @@ -1,50 +0,0 @@ -read_verilog << EOT -module top(...); -input clk; -input d; -input sr; -output reg q0, q1, q2, q3, q4, q5; - -initial q0 = 1'b0; -initial q1 = 1'b0; -initial q2 = 1'b1; -initial q3 = 1'b1; -initial q4 = 1'bx; -initial q5 = 1'bx; - -always @(posedge clk) begin - q0 <= sr ? 1'b0 : d; - q1 <= sr ? 1'b1 : d; - q2 <= sr ? 1'b0 : d; - q3 <= sr ? 1'b1 : d; - q4 <= sr ? 1'b0 : d; - q5 <= sr ? 1'b1 : d; -end - -endmodule -EOT - -proc -simplemap -design -save ref - -dff2dffs -clean - -select -assert-count 1 w:q0 %x t:$_SDFF_PP0_ %i -select -assert-count 1 w:q1 %x t:$_SDFF_PP1_ %i -select -assert-count 1 w:q2 %x t:$_SDFF_PP0_ %i -select -assert-count 1 w:q3 %x t:$_SDFF_PP1_ %i -select -assert-count 1 w:q4 %x t:$_SDFF_PP0_ %i -select -assert-count 1 w:q5 %x t:$_SDFF_PP1_ %i - -design -load ref -dff2dffs -match-init -clean - -select -assert-count 1 w:q0 %x t:$_SDFF_PP0_ %i -select -assert-count 0 w:q1 %x t:$_SDFF_PP1_ %i -select -assert-count 0 w:q2 %x t:$_SDFF_PP0_ %i -select -assert-count 1 w:q3 %x t:$_SDFF_PP1_ %i -select -assert-count 1 w:q4 %x t:$_SDFF_PP0_ %i -select -assert-count 1 w:q5 %x t:$_SDFF_PP1_ %i |