diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2020-04-13 15:16:51 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2020-04-13 15:16:51 -0700 |
| commit | c6afce763807862305c4ade28ef5bb72a4b078f6 (patch) | |
| tree | 8a54788e390e2c13aa0022549081caaff3d70c9f /tests/techmap/zinit.ys | |
| parent | 091297b9ee9c7874f17abb855f6c612c448cec70 (diff) | |
| download | yosys-c6afce763807862305c4ade28ef5bb72a4b078f6.tar.gz yosys-c6afce763807862305c4ade28ef5bb72a4b078f6.tar.bz2 yosys-c6afce763807862305c4ade28ef5bb72a4b078f6.zip | |
zinit: fix review comments from @mwkmwkmwk
Diffstat (limited to 'tests/techmap/zinit.ys')
| -rw-r--r-- | tests/techmap/zinit.ys | 35 |
1 files changed, 31 insertions, 4 deletions
diff --git a/tests/techmap/zinit.ys b/tests/techmap/zinit.ys index caeab69d3..c74218f7c 100644 --- a/tests/techmap/zinit.ys +++ b/tests/techmap/zinit.ys @@ -1,5 +1,5 @@ read_verilog -icells <<EOT -module top(input C, R, input [1:0] D, (* init = {12{1'b1}} *) output [11:0] Q); +module top(input C, R, input [1:0] D, (* init = {2'b10, 2'b01, 1'b1, {8{1'b1}}} *) output [12:0] Q); (* init = 1'b1 *) wire unused; @@ -13,11 +13,38 @@ $_DFF_PN1_ dff5 (.C(C), .D(D[0]), .R(R), .Q(Q[5])); $_DFF_PP0_ dff6 (.C(C), .D(D[0]), .R(R), .Q(Q[6])); $_DFF_PP1_ dff7 (.C(C), .D(D[0]), .R(R), .Q(Q[7])); -$adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'd2)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[9:8])); -$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'd1)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[11:10])); +$adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[10:9])); +$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11])); endmodule EOT -equiv_opt -map +/simcells.v -multiclock zinit +equiv_opt -assert -map +/simcells.v -multiclock zinit design -load postopt +select -assert-count 20 t:$_NOT_ select -assert-count 1 w:unused a:init %i +select -assert-count 1 w:Q a:init=13'bxxxx1xxxxxxxx %i + + +design -reset +read_verilog -icells <<EOT +module top(input C, R, input [1:0] D, (* init = {2'bx0, 2'b0x, 1'b1, {8{1'b0}}} *) output [12:0] Q); + +(* init = 1'b1 *) +wire unused; + +$_DFF_NN0_ dff0 (.C(C), .D(D[0]), .R(R), .Q(Q[0])); +$_DFF_NN1_ dff1 (.C(C), .D(D[0]), .R(R), .Q(Q[1])); +$_DFF_NP0_ dff2 (.C(C), .D(D[0]), .R(R), .Q(Q[2])); +$_DFF_NP1_ dff3 (.C(C), .D(D[0]), .R(R), .Q(Q[3])); +$_DFF_PN0_ dff4 (.C(C), .D(D[0]), .R(R), .Q(Q[4])); +$_DFF_PN1_ dff5 (.C(C), .D(D[0]), .R(R), .Q(Q[5])); +$_DFF_PP0_ dff6 (.C(C), .D(D[0]), .R(R), .Q(Q[6])); +$_DFF_PP1_ dff7 (.C(C), .D(D[0]), .R(R), .Q(Q[7])); + +$adff #(.WIDTH(2), .CLK_POLARITY(1), .ARST_POLARITY(1'b0), .ARST_VALUE(2'b10)) dff8 (.CLK(C), .ARST(R), .D(D), .Q(Q[10:9])); +$adff #(.WIDTH(2), .CLK_POLARITY(0), .ARST_POLARITY(1'b1), .ARST_VALUE(2'b01)) dff9 (.CLK(C), .ARST(R), .D(D), .Q(Q[12:11])); +endmodule +EOT +select -assert-count 0 t:$_NOT_ +select -assert-count 1 w:unused a:init %i +select -assert-count 1 w:Q a:init=13'bx00x100000000 %i |