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| author | Clifford Wolf <clifford@clifford.at> | 2014-02-21 12:06:40 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-02-21 12:06:40 +0100 |
| commit | 81b3f52519d388f252405fa7cc7472ca9e51bc49 (patch) | |
| tree | 26d1faee61bcac2276307c8919b20ca493dfedd2 /tests/techmap/mem_simple_4x1_cells.v | |
| parent | 79f8944811cba40ca0f3bda98ab951395d24fa0b (diff) | |
| download | yosys-81b3f52519d388f252405fa7cc7472ca9e51bc49.tar.gz yosys-81b3f52519d388f252405fa7cc7472ca9e51bc49.tar.bz2 yosys-81b3f52519d388f252405fa7cc7472ca9e51bc49.zip | |
Added tests/techmap/mem_simple_4x1
Diffstat (limited to 'tests/techmap/mem_simple_4x1_cells.v')
| -rw-r--r-- | tests/techmap/mem_simple_4x1_cells.v | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/techmap/mem_simple_4x1_cells.v b/tests/techmap/mem_simple_4x1_cells.v new file mode 100644 index 000000000..7ecdd2dee --- /dev/null +++ b/tests/techmap/mem_simple_4x1_cells.v @@ -0,0 +1,13 @@ +module MEM4X1 (CLK, RD_ADDR, RD_DATA, WR_ADDR, WR_DATA, WR_EN); + input CLK, WR_DATA, WR_EN; + input [3:0] RD_ADDR, WR_ADDR; + output reg RD_DATA; + + reg [15:0] memory; + + always @(posedge CLK) begin + if (WR_EN) + memory[WR_ADDR] <= WR_DATA; + RD_DATA <= memory[RD_ADDR]; + end +endmodule |