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author | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-06-30 15:30:59 +0200 |
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committer | Marcelina KoĆcielnicka <mwk@0x04.net> | 2020-07-01 01:57:15 +0200 |
commit | 6b42819a37a02ee4cc0724f54cbbd3ac996ca0a8 (patch) | |
tree | c9eb5f696a1d0c59e7100b43a61825033a48e6a2 /tests/techmap/dfflegalize_sr.ys | |
parent | e3564b4502b05f58e6e9d9fc96603dd8a5a0b2d2 (diff) | |
download | yosys-6b42819a37a02ee4cc0724f54cbbd3ac996ca0a8.tar.gz yosys-6b42819a37a02ee4cc0724f54cbbd3ac996ca0a8.tar.bz2 yosys-6b42819a37a02ee4cc0724f54cbbd3ac996ca0a8.zip |
dfflegalize: Add tests.
Diffstat (limited to 'tests/techmap/dfflegalize_sr.ys')
-rw-r--r-- | tests/techmap/dfflegalize_sr.ys | 74 |
1 files changed, 74 insertions, 0 deletions
diff --git a/tests/techmap/dfflegalize_sr.ys b/tests/techmap/dfflegalize_sr.ys new file mode 100644 index 000000000..a75068ae0 --- /dev/null +++ b/tests/techmap/dfflegalize_sr.ys @@ -0,0 +1,74 @@ +read_verilog -icells <<EOT + +module sr(input R, S, output [2:0] Q); +$_SR_PP_ ff0 (.R(R), .S(S), .Q(Q[0])); +$_SR_PN_ ff1 (.R(R), .S(S), .Q(Q[1])); +$_SR_NP_ ff2 (.R(R), .S(S), .Q(Q[2])); +endmodule + +EOT + +design -save orig +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_SR_PP_ x +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP0_ x +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCH_PP1_ x +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DLATCHSR_PPP_ x +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSR_PPP_ x +equiv_opt -assert -multiclock -map +/simcells.v dfflegalize -cell $_DFFSRE_PPPP_ x + + +# Convert everything to SRs. + +design -load orig +dfflegalize -cell $_SR_PP_ x + +select -assert-count 2 t:$_NOT_ +select -assert-count 3 t:$_SR_PP_ +select -assert-none t:$_SR_PP_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to ADLATCHs. + +design -load orig +dfflegalize -cell $_DLATCH_PP0_ x + +select -assert-count 2 t:$_NOT_ +select -assert-count 3 t:$_DLATCH_PP0_ +select -assert-none t:$_DLATCH_PP0_ t:$_NOT_ %% %n t:* %i + +design -load orig +dfflegalize -cell $_DLATCH_PP1_ x + +select -assert-count 8 t:$_NOT_ +select -assert-count 3 t:$_DLATCH_PP1_ +select -assert-none t:$_DLATCH_PP1_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to DLATCHSRs. + +design -load orig +dfflegalize -cell $_DLATCHSR_PPP_ x + +select -assert-count 2 t:$_NOT_ +select -assert-count 3 t:$_DLATCHSR_PPP_ +select -assert-none t:$_DLATCHSR_PPP_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to DFFSRs. + +design -load orig +dfflegalize -cell $_DFFSR_PPP_ x + +select -assert-count 2 t:$_NOT_ +select -assert-count 3 t:$_DFFSR_PPP_ +select -assert-none t:$_DFFSR_PPP_ t:$_NOT_ %% %n t:* %i + + +# Convert everything to DFFSREs. + +design -load orig +dfflegalize -cell $_DFFSRE_PPPP_ x + +select -assert-count 2 t:$_NOT_ +select -assert-count 3 t:$_DFFSRE_PPPP_ +select -assert-none t:$_DFFSRE_PPPP_ t:$_NOT_ %% %n t:* %i |