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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-27 11:42:05 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-27 11:42:05 +0200 |
| commit | b24f73775983eb7a30d50f608ccc8702e54c57c3 (patch) | |
| tree | 1ac774a5810f821740f6c721e348a34b8c9408ac /tests/sva/basic05.vhd | |
| parent | 90d8329f642e710e8d4ce358cfb9543b85bcd822 (diff) | |
| download | yosys-b24f73775983eb7a30d50f608ccc8702e54c57c3.tar.gz yosys-b24f73775983eb7a30d50f608ccc8702e54c57c3.tar.bz2 yosys-b24f73775983eb7a30d50f608ccc8702e54c57c3.zip | |
Improve SVA tests, add Makefile and scripts
Diffstat (limited to 'tests/sva/basic05.vhd')
| -rw-r--r-- | tests/sva/basic05.vhd | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/sva/basic05.vhd b/tests/sva/basic05.vhd index 930f1ba22..8d42f71e8 100644 --- a/tests/sva/basic05.vhd +++ b/tests/sva/basic05.vhd @@ -10,9 +10,9 @@ entity demo is end entity; architecture rtl of demo is - signal read : std_logic; - signal write : std_logic; - signal ready : std_logic; + signal read : std_logic := '0'; + signal write : std_logic := '0'; + signal ready : std_logic := '0'; begin process (clock) begin if (rising_edge(clock)) then |