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| author | Clifford Wolf <clifford@clifford.at> | 2017-07-22 16:35:46 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2017-07-22 16:35:46 +0200 |
| commit | 84f15260b5f3d328c75ee385d2fdc2861b4e8f59 (patch) | |
| tree | 87917cc11e9d0d69751ffaed5836ed970d532e26 /tests/sva/basic02.sv | |
| parent | 5be535517cfe9ce4c664e95eb02684305fc268e3 (diff) | |
| download | yosys-84f15260b5f3d328c75ee385d2fdc2861b4e8f59.tar.gz yosys-84f15260b5f3d328c75ee385d2fdc2861b4e8f59.tar.bz2 yosys-84f15260b5f3d328c75ee385d2fdc2861b4e8f59.zip | |
Add more SVA test cases for future Verific work
Diffstat (limited to 'tests/sva/basic02.sv')
| -rw-r--r-- | tests/sva/basic02.sv | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/sva/basic02.sv b/tests/sva/basic02.sv index 6100c50ae..cf2d72ae7 100644 --- a/tests/sva/basic02.sv +++ b/tests/sva/basic02.sv @@ -13,4 +13,4 @@ module top_properties (input logic clock, read, write, ready); a_wr: assert property ( @(posedge clock) write |-> ready ); endmodule -bind top top_properties inst (.*); +bind top top_properties properties_inst (.*); |