aboutsummaryrefslogtreecommitdiffstats
path: root/tests/simple_abc9
diff options
context:
space:
mode:
authorEddie Hung <eddie@fpgeh.com>2019-04-23 16:11:14 -0700
committerEddie Hung <eddie@fpgeh.com>2019-04-23 16:11:14 -0700
commitbfd71e09906096c72039beebb1b3b6a79dd6b36c (patch)
tree99304bae98b5c9f462683c77ffcc53f1ca5a5076 /tests/simple_abc9
parent9d122d3c51575fe6803729e8f953141edb3b12c3 (diff)
downloadyosys-bfd71e09906096c72039beebb1b3b6a79dd6b36c.tar.gz
yosys-bfd71e09906096c72039beebb1b3b6a79dd6b36c.tar.bz2
yosys-bfd71e09906096c72039beebb1b3b6a79dd6b36c.zip
Fix abc9 with (* keep *) wires
Diffstat (limited to 'tests/simple_abc9')
-rw-r--r--tests/simple_abc9/abc9.v38
1 files changed, 38 insertions, 0 deletions
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index eca340693..f37d975ff 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -104,3 +104,41 @@ always @(io or oe)
assign io[3:0] = oe ? ~latch[3:0] : 4'bz;
assign io[7:4] = !oe ? {latch[4], latch[7:3]} : 4'bz;
endmodule
+
+module abc9_test015(input a, output b, input c);
+assign b = ~a;
+(* keep *) wire d;
+assign d = ~c;
+endmodule
+
+module abc9_test016(input a, output b);
+assign b = ~a;
+(* keep *) reg c;
+always @* c <= ~a;
+endmodule
+
+module abc9_test017(input a, output b);
+assign b = ~a;
+(* keep *) reg c;
+always @* c = b;
+endmodule
+
+module abc9_test018(input a, output b, output c);
+assign b = ~a;
+(* keep *) wire [1:0] d;
+assign c = &d;
+endmodule
+
+module abc9_test019(input a, output b);
+assign b = ~a;
+(* keep *) reg [1:0] c;
+reg d;
+always @* d <= &c;
+endmodule
+
+module abc9_test020(input a, output b);
+assign b = ~a;
+(* keep *) reg [1:0] c;
+(* keep *) reg d;
+always @* d <= &c;
+endmodule