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authorEddie Hung <eddie@fpgeh.com>2019-11-21 16:15:25 -0800
committerEddie Hung <eddie@fpgeh.com>2019-11-21 16:15:25 -0800
commit5a30e3ac3ba6435ebf9db0f8acfba61e9ee73ad7 (patch)
tree9f6ee2debc233e178be133c218a8b021389d2c0e /tests/simple_abc9
parent911a152b39959137b26e68581a6cacbcabb4ab1d (diff)
parent1cc106452fb25d082ca9491c24df97cc51d4b992 (diff)
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Merge branch 'eddie/xaig_dff_adff' into xaig_dff
Diffstat (limited to 'tests/simple_abc9')
-rw-r--r--tests/simple_abc9/abc9.v17
1 files changed, 14 insertions, 3 deletions
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v
index 13c505eec..596a52501 100644
--- a/tests/simple_abc9/abc9.v
+++ b/tests/simple_abc9/abc9.v
@@ -268,12 +268,23 @@ assign o = { 1'b1, 1'bx };
assign p = { 1'b1, 1'bx, 1'b0 };
endmodule
-module abc9_test029(input clk1, clk2, d, output reg q1, q2);
+module abc9_test029(input clk, d, r, output reg q);
+always @(posedge clk or posedge r)
+ if (r) q <= 1'b0;
+ else q <= d;
+endmodule
+
+module abc9_test030(input clk, d, r, output reg q);
+always @(negedge clk or posedge r)
+ if (r) q <= 1'b1;
+ else q <= d;
+endmodule
+
+module abc9_test032(input clk1, clk2, d, output reg q1, q2);
always @(posedge clk1) q1 <= d;
always @(negedge clk2) q2 <= q1;
endmodule
-module abc9_test030(input clk, d, output reg q1, q2);
+module abc9_test033(input clk, d, output reg q1, q2);
always @(posedge clk) q1 <= d;
always @(posedge clk) q2 <= q1;
-endmodule