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| author | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 16:52:55 -0800 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-11-22 16:52:55 -0800 |
| commit | 74ea4381362d4f402e7fc262b960e14122128303 (patch) | |
| tree | 659e822e4ff958645af8f515b58ae75f906d1311 /tests/simple_abc9/abc9.v | |
| parent | 81548d1ef988d10007706c36df5885f8557de74a (diff) | |
| download | yosys-74ea4381362d4f402e7fc262b960e14122128303.tar.gz yosys-74ea4381362d4f402e7fc262b960e14122128303.tar.bz2 yosys-74ea4381362d4f402e7fc262b960e14122128303.zip | |
Add testcase for signal used as part input part output
Diffstat (limited to 'tests/simple_abc9/abc9.v')
| -rw-r--r-- | tests/simple_abc9/abc9.v | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/tests/simple_abc9/abc9.v b/tests/simple_abc9/abc9.v index 6bdd3bc32..8314af211 100644 --- a/tests/simple_abc9/abc9.v +++ b/tests/simple_abc9/abc9.v @@ -289,3 +289,8 @@ module abc9_test033(input clk, d, output reg q1, q2); always @(posedge clk) q1 <= d; always @(posedge clk) q2 <= q1; endmodule + +module abc9_test034(input clk, d, output reg [1:0] q); +always @(posedge clk) q[0] <= d; +always @(negedge clk) q[1] <= q[0]; +endmodule |