diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2020-03-09 11:51:57 -0700 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2020-03-09 11:51:57 -0700 |
| commit | d23acf8c61538aacc9816358f16f0293de5b064d (patch) | |
| tree | cc758f4e70eb79512f528d75c2d73d0742776f68 /tests/simple | |
| parent | 282d331e7e5783214eb4bc9b2e667f0d67ddc5fe (diff) | |
| parent | a7cc4673c3f75f414a82c81a507da5042bba361f (diff) | |
| download | yosys-d23acf8c61538aacc9816358f16f0293de5b064d.tar.gz yosys-d23acf8c61538aacc9816358f16f0293de5b064d.tar.bz2 yosys-d23acf8c61538aacc9816358f16f0293de5b064d.zip | |
Merge pull request #1747 from YosysHQ/claire/partselfix
Fix partsel expr bit width handling and add test case
Diffstat (limited to 'tests/simple')
| -rw-r--r-- | tests/simple/partsel.v | 4 |
1 files changed, 4 insertions, 0 deletions
diff --git a/tests/simple/partsel.v b/tests/simple/partsel.v index 7461358ad..83493fcb0 100644 --- a/tests/simple/partsel.v +++ b/tests/simple/partsel.v @@ -60,3 +60,7 @@ always @(posedge clk) begin end endmodule + +module partsel_test003(input [2:0] a, b, input [31:0] din, output [3:0] dout); +assign dout = din[a*b +: 2]; +endmodule |