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| author | Clifford Wolf <clifford@clifford.at> | 2013-11-22 17:33:59 +0100 |
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| committer | Clifford Wolf <clifford@clifford.at> | 2013-11-22 17:33:59 +0100 |
| commit | bf501b9ba3f01fa00d895a6681dcfafcfb51b248 (patch) | |
| tree | fdce96a2bd9685c73929126cc4553c5d31ebd688 /tests/simple | |
| parent | 7b9ca46f8d23d3031482aae5ec640f97d67b7e97 (diff) | |
| download | yosys-bf501b9ba3f01fa00d895a6681dcfafcfb51b248.tar.gz yosys-bf501b9ba3f01fa00d895a6681dcfafcfb51b248.tar.bz2 yosys-bf501b9ba3f01fa00d895a6681dcfafcfb51b248.zip | |
Started to write on AppNote 010: Verilog to BLIF
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