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| author | Clifford Wolf <clifford@clifford.at> | 2019-06-19 13:53:07 +0200 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2019-06-19 13:53:07 +0200 |
| commit | 5a1f1caa44fb3f4427813acab61aaecc06bae7ba (patch) | |
| tree | 3cceea7d49a6ae44e5ab765e0bd11fecfee6b47b /tests/simple | |
| parent | c330379870a48209534807d1c021ce2a20ccf880 (diff) | |
| parent | fa5fc3f6afd9eb27c1f52244b60cbeb77aa2e26c (diff) | |
| download | yosys-5a1f1caa44fb3f4427813acab61aaecc06bae7ba.tar.gz yosys-5a1f1caa44fb3f4427813acab61aaecc06bae7ba.tar.bz2 yosys-5a1f1caa44fb3f4427813acab61aaecc06bae7ba.zip | |
Merge pull request #1105 from YosysHQ/clifford/fixlogicinit
Improve handling of initial/default values
Diffstat (limited to 'tests/simple')
| -rw-r--r-- | tests/simple/defvalue.sv | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/simple/defvalue.sv b/tests/simple/defvalue.sv new file mode 100644 index 000000000..b0a087ecb --- /dev/null +++ b/tests/simple/defvalue.sv @@ -0,0 +1,22 @@ +module top(input clock, input [3:0] delta, output [3:0] cnt1, cnt2); + cnt #(1) foo (.clock, .cnt(cnt1), .delta); + cnt #(2) bar (.clock, .cnt(cnt2)); +endmodule + +module cnt #( + parameter integer initval = 0 +) ( + input clock, + output logic [3:0] cnt = initval, +`ifdef __ICARUS__ + input [3:0] delta +`else + input [3:0] delta = 10 +`endif +); +`ifdef __ICARUS__ + assign (weak0, weak1) delta = 10; +`endif + always @(posedge clock) + cnt <= cnt + delta; +endmodule |