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| author | Zachary Snow <zach@zachjs.com> | 2021-03-27 15:59:48 -0400 |
|---|---|---|
| committer | Zachary Snow <zachary.j.snow@gmail.com> | 2021-05-25 16:15:57 -0400 |
| commit | 15f35d6754af619accdf63030e0a5ad3085cec16 (patch) | |
| tree | 197ef49a4ae4f1c05448f5398ea71ee90117dbf6 /tests/simple | |
| parent | 3514c92dc42644d64dca2167c05096d10891de69 (diff) | |
| download | yosys-15f35d6754af619accdf63030e0a5ad3085cec16.tar.gz yosys-15f35d6754af619accdf63030e0a5ad3085cec16.tar.bz2 yosys-15f35d6754af619accdf63030e0a5ad3085cec16.zip | |
sv: support remaining assignment operators
- Add support for: *=, /=, %=, <<=, >>=, <<<=, >>>=
- Unify existing support for: +=, -=, &=, |=, ^=
Diffstat (limited to 'tests/simple')
| -rw-r--r-- | tests/simple/asgn_binop.sv | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/tests/simple/asgn_binop.sv b/tests/simple/asgn_binop.sv new file mode 100644 index 000000000..b134e5697 --- /dev/null +++ b/tests/simple/asgn_binop.sv @@ -0,0 +1,23 @@ +`define TEST(name, asgnop)\ + module test_``name ( \ + input logic [3:0] a, b, \ + output logic [3:0] c \ + ); \ + always @* begin \ + c = a; \ + c asgnop b; \ + end \ + endmodule + +`TEST(add, +=) +`TEST(sub, -=) +`TEST(mul, *=) +`TEST(div, /=) +`TEST(mod, %=) +`TEST(bit_and, &=) +`TEST(bit_or , |=) +`TEST(bit_xor, ^=) +`TEST(shl, <<=) +`TEST(shr, >>=) +`TEST(sshl, <<<=) +`TEST(sshr, >>>=) |