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| author | Clifford Wolf <clifford@clifford.at> | 2014-06-25 10:05:36 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-06-25 10:05:36 +0200 |
| commit | 076182c34e34b5e59eb5d89d5001f7547102bb4d (patch) | |
| tree | dd06896f4ab771bf1af11045a9f4c72e53c3e44c /tests/simple | |
| parent | 4fc43d19324eabcfe3a3788743a212ae684509cd (diff) | |
| download | yosys-076182c34e34b5e59eb5d89d5001f7547102bb4d.tar.gz yosys-076182c34e34b5e59eb5d89d5001f7547102bb4d.tar.bz2 yosys-076182c34e34b5e59eb5d89d5001f7547102bb4d.zip | |
Fixed handling of mixed real/int ternary expressions
Diffstat (limited to 'tests/simple')
| -rw-r--r-- | tests/simple/realexpr.v | 9 |
1 files changed, 6 insertions, 3 deletions
diff --git a/tests/simple/realexpr.v b/tests/simple/realexpr.v index 2adffe2dd..5b756e6be 100644 --- a/tests/simple/realexpr.v +++ b/tests/simple/realexpr.v @@ -13,9 +13,12 @@ module demo_001(y1, y2, y3, y4); assign y4 = p4 + 0.2; endmodule -module demo_002(y1); - output [3:0] y1; +module demo_002(y0, y1, y2, y3); + output [63:0] y0, y1, y2, y3; - assign y1 = 1'bx >= (-1 * -1.17); + assign y0 = 1'bx >= (-1 * -1.17); + assign y1 = 1 ? 1 ? -1 : 'd0 : 0.0; + assign y2 = 1 ? -1 : 1 ? 'd0 : 0.0; + assign y3 = 1 ? -1 : 'd0; endmodule |