diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-05-01 18:09:38 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-05-01 18:09:38 -0700 |
| commit | 31ff0d8ef529a1ddfa37e4b68017e4e433399da7 (patch) | |
| tree | 921a3a801a4e7bc9d8998b0aa7f21506db7881e6 /tests/simple/xfirrtl | |
| parent | e97178a888cebc6acacb8f8f2c68d4f9743a9284 (diff) | |
| parent | f86d153cef724af9d30e4139783a7e14d7ba0a19 (diff) | |
| download | yosys-31ff0d8ef529a1ddfa37e4b68017e4e433399da7.tar.gz yosys-31ff0d8ef529a1ddfa37e4b68017e4e433399da7.tar.bz2 yosys-31ff0d8ef529a1ddfa37e4b68017e4e433399da7.zip | |
Merge remote-tracking branch 'origin/master' into eddie/synth_xilinx_fine
Diffstat (limited to 'tests/simple/xfirrtl')
| -rw-r--r-- | tests/simple/xfirrtl | 1 |
1 files changed, 1 insertions, 0 deletions
diff --git a/tests/simple/xfirrtl b/tests/simple/xfirrtl index 50d693513..ba61a4476 100644 --- a/tests/simple/xfirrtl +++ b/tests/simple/xfirrtl @@ -16,6 +16,7 @@ operators.v $pow partsel.v drops modules process.v drops modules realexpr.v drops modules +retime.v Initial value (11110101) for (retime_test.ff) not supported scopes.v original verilog issues ( -x where x isn't declared signed) sincos.v $adff specify.v no code (empty module generates error |