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| author | Claire Xenia Wolf <claire@clairexen.net> | 2021-09-22 17:34:20 +0200 |
|---|---|---|
| committer | Claire Xenia Wolf <claire@clairexen.net> | 2021-09-23 14:54:28 +0200 |
| commit | 15fb0107dcdfcf98c56f229727c7cd701ff9b4b3 (patch) | |
| tree | 53d8c5a6530545103701e0842d926b40a657748c /tests/simple/module_scope_case.v | |
| parent | 3931b3a03f65965daca20b1228d8882192e74650 (diff) | |
| download | yosys-15fb0107dcdfcf98c56f229727c7cd701ff9b4b3.tar.gz yosys-15fb0107dcdfcf98c56f229727c7cd701ff9b4b3.tar.bz2 yosys-15fb0107dcdfcf98c56f229727c7cd701ff9b4b3.zip | |
Fix "make vgtest" so it runs to the end (but now it fails ;)
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
Diffstat (limited to 'tests/simple/module_scope_case.v')
| -rw-r--r-- | tests/simple/module_scope_case.v | 8 |
1 files changed, 4 insertions, 4 deletions
diff --git a/tests/simple/module_scope_case.v b/tests/simple/module_scope_case.v index 1472b6912..bceba4424 100644 --- a/tests/simple/module_scope_case.v +++ b/tests/simple/module_scope_case.v @@ -1,11 +1,11 @@ -module top( +module module_scope_case_top( input wire x, output reg y ); always @* begin - case (top.x) - 1: top.y = 0; - 0: top.y = 1; + case (module_scope_case_top.x) + 1: module_scope_case_top.y = 0; + 0: module_scope_case_top.y = 1; endcase end endmodule |