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| author | Clifford Wolf <clifford@clifford.at> | 2014-03-17 01:56:00 +0100 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2014-03-17 01:56:00 +0100 |
| commit | a67cd2d4a284cb945af6d477cc215cef7bdd22a8 (patch) | |
| tree | 2be5f13ffe5ecdec4fc365bba955ccd83258254c /tests/simple/mem_arst.v | |
| parent | acda74c12cd39ae1a17d15f472728b49ad584e91 (diff) | |
| download | yosys-a67cd2d4a284cb945af6d477cc215cef7bdd22a8.tar.gz yosys-a67cd2d4a284cb945af6d477cc215cef7bdd22a8.tar.bz2 yosys-a67cd2d4a284cb945af6d477cc215cef7bdd22a8.zip | |
Progress in Verific bindings
Diffstat (limited to 'tests/simple/mem_arst.v')
| -rw-r--r-- | tests/simple/mem_arst.v | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/simple/mem_arst.v b/tests/simple/mem_arst.v index 4022f57cd..9bd38fcb3 100644 --- a/tests/simple/mem_arst.v +++ b/tests/simple/mem_arst.v @@ -10,7 +10,7 @@ module MyMem #( output [DataWidth-1:0] Data_o, input WR_i); - reg Data_o; + reg [DataWidth-1:0] Data_o; localparam Size = 2**AddrWidth; |