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author | Zachary Snow <zach@zachjs.com> | 2020-07-31 20:13:05 -0600 |
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committer | Zachary Snow <zach@zachjs.com> | 2020-07-31 20:32:47 -0600 |
commit | c3e95eb1abb35fff98111b3a98e2fa7766754552 (patch) | |
tree | 832d35348353f01a71a58309ef61e6b076c8f8fb /tests/simple/generate.v | |
parent | c39ebe6ae0e41cf9a84da852fa3cf9f71937a9b2 (diff) | |
download | yosys-c3e95eb1abb35fff98111b3a98e2fa7766754552.tar.gz yosys-c3e95eb1abb35fff98111b3a98e2fa7766754552.tar.bz2 yosys-c3e95eb1abb35fff98111b3a98e2fa7766754552.zip |
Fix generate scoping issues
- expand_genblock defers prefixing of items within named sub-blocks
- Allow partially-qualified references to local scopes
- Handle shadowing within generate blocks
- Resolve generate scope references within tasks and functions
- Apply generate scoping to genvars
- Resolves #2214, resolves #1456
Diffstat (limited to 'tests/simple/generate.v')
-rw-r--r-- | tests/simple/generate.v | 85 |
1 files changed, 85 insertions, 0 deletions
diff --git a/tests/simple/generate.v b/tests/simple/generate.v index 0e353ad9b..dcd450e47 100644 --- a/tests/simple/generate.v +++ b/tests/simple/generate.v @@ -159,3 +159,88 @@ generate end endgenerate endmodule + +// ------------------------------------------ + +module gen_test7; + reg [2:0] out1; + reg [2:0] out2; + wire [2:0] out3; + generate + begin : cond + reg [2:0] sub_out1; + reg [2:0] sub_out2; + wire [2:0] sub_out3; + initial begin : init + reg signed [31:0] x; + x = 2 ** 2; + out1 = x; + sub_out1 = x; + end + always @* begin : proc + reg signed [31:0] x; + x = 2 ** 1; + out2 = x; + sub_out2 = x; + end + genvar x; + for (x = 0; x < 3; x = x + 1) begin + assign out3[x] = 1; + assign sub_out3[x] = 1; + end + end + endgenerate + +// `define VERIFY +`ifdef VERIFY + assert property (out1 == 4); + assert property (out2 == 2); + assert property (out3 == 7); + assert property (cond.sub_out1 == 4); + assert property (cond.sub_out2 == 2); + assert property (cond.sub_out3 == 7); +`endif +endmodule + +// ------------------------------------------ + +module gen_test8; + +// `define VERIFY +`ifdef VERIFY + `define ASSERT(expr) assert property (expr); +`else + `define ASSERT(expr) +`endif + + wire [1:0] x = 2'b11; + generate + begin : A + wire [1:0] x; + begin : B + wire [1:0] x = 2'b00; + `ASSERT(x == 0) + `ASSERT(A.x == 2) + `ASSERT(A.C.x == 1) + `ASSERT(A.B.x == 0) + end + begin : C + wire [1:0] x = 2'b01; + `ASSERT(x == 1) + `ASSERT(A.x == 2) + `ASSERT(A.C.x == 1) + `ASSERT(A.B.x == 0) + end + assign x = B.x ^ 2'b11 ^ C.x; + `ASSERT(x == 2) + `ASSERT(A.x == 2) + `ASSERT(A.C.x == 1) + `ASSERT(A.B.x == 0) + end + endgenerate + + `ASSERT(x == 3) + `ASSERT(A.x == 2) + `ASSERT(A.C.x == 1) + `ASSERT(A.B.x == 0) +endmodule |