Merge pull request #805 from eddiehung/dff_init

write_verilog to write initial statement for initial flop state

1 files changed, 42 insertions, 0 deletions

diff --git a/tests/simple/dff_init.v b/tests/simple/dff_init.v
new file mode 100644
index 000000000..be947042e
--- /dev/null
+++ b/tests/simple/dff_init.v
@@ -0,0 +1,42 @@
+module dff0_test(n1, n1_inv, clk);
+  input clk;
+  output n1;
+  reg n1 = 32'd0;
+  output n1_inv;
+  always @(posedge clk)
+      n1 <= n1_inv;
+  assign n1_inv = ~n1;
+endmodule
+
+module dff1_test(n1, n1_inv, clk);
+  input clk;
+  (* init = 32'd1 *)
+  output n1;
+  reg n1 = 32'd1;
+  output n1_inv;
+  always @(posedge clk)
+      n1 <= n1_inv;
+  assign n1_inv = ~n1;
+endmodule
+
+module dff0a_test(n1, n1_inv, clk);
+  input clk;
+  (* init = 32'd0 *) // Must be consistent with reg initialiser below
+  output n1;
+  reg n1 = 32'd0;
+  output n1_inv;
+  always @(posedge clk)
+      n1 <= n1_inv;
+  assign n1_inv = ~n1;
+endmodule
+
+module dff1a_test(n1, n1_inv, clk);
+  input clk;
+  (* init = 32'd1 *) // Must be consistent with reg initialiser below
+  output n1;
+  reg n1 = 32'd1;
+  output n1_inv;
+  always @(posedge clk)
+      n1 <= n1_inv;
+  assign n1_inv = ~n1;
+endmodule