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author | Maciej Kurc <mkurc@antmicro.com> | 2019-06-03 09:12:51 +0200 |
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committer | Maciej Kurc <mkurc@antmicro.com> | 2019-06-03 09:25:20 +0200 |
commit | 5739cf52650ccb3627868d9c9d7e02888efad12b (patch) | |
tree | cb3e467303121061eeff62393a3c45bf76c03860 /tests/simple/attrib06_operator_suffix.v | |
parent | a6cadf6318f4eff6197d6c6f0e052c2417689f38 (diff) | |
download | yosys-5739cf52650ccb3627868d9c9d7e02888efad12b.tar.gz yosys-5739cf52650ccb3627868d9c9d7e02888efad12b.tar.bz2 yosys-5739cf52650ccb3627868d9c9d7e02888efad12b.zip |
Added tests for attributes
Signed-off-by: Maciej Kurc <mkurc@antmicro.com>
Diffstat (limited to 'tests/simple/attrib06_operator_suffix.v')
-rw-r--r-- | tests/simple/attrib06_operator_suffix.v | 23 |
1 files changed, 23 insertions, 0 deletions
diff --git a/tests/simple/attrib06_operator_suffix.v b/tests/simple/attrib06_operator_suffix.v new file mode 100644 index 000000000..e21173c58 --- /dev/null +++ b/tests/simple/attrib06_operator_suffix.v @@ -0,0 +1,23 @@ +module bar(clk, rst, inp_a, inp_b, out); + input wire clk; + input wire rst; + input wire [7:0] inp_a; + input wire [7:0] inp_b; + output reg [7:0] out; + + always @(posedge clk) + if (rst) out <= 0; + else out <= inp_a + (* ripple_adder *) inp_b; + +endmodule + +module foo(clk, rst, inp_a, inp_b, out); + input wire clk; + input wire rst; + input wire [7:0] inp_a; + input wire [7:0] inp_b; + output wire [7:0] out; + + bar bar_instance (clk, rst, inp_a, inp_b, out); +endmodule + |