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authorClaire Xenia Wolf <claire@clairexen.net>2021-09-22 17:34:20 +0200
committerClaire Xenia Wolf <claire@clairexen.net>2021-09-23 14:54:28 +0200
commit15fb0107dcdfcf98c56f229727c7cd701ff9b4b3 (patch)
tree53d8c5a6530545103701e0842d926b40a657748c /tests/simple/attrib01_module.v
parent3931b3a03f65965daca20b1228d8882192e74650 (diff)
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Fix "make vgtest" so it runs to the end (but now it fails ;)
Signed-off-by: Claire Xenia Wolf <claire@clairexen.net>
Diffstat (limited to 'tests/simple/attrib01_module.v')
-rw-r--r--tests/simple/attrib01_module.v6
1 files changed, 3 insertions, 3 deletions
diff --git a/tests/simple/attrib01_module.v b/tests/simple/attrib01_module.v
index adef34f5b..d6e36fb80 100644
--- a/tests/simple/attrib01_module.v
+++ b/tests/simple/attrib01_module.v
@@ -1,4 +1,4 @@
-module bar(clk, rst, inp, out);
+module attrib01_bar(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
@@ -10,12 +10,12 @@ module bar(clk, rst, inp, out);
endmodule
-module foo(clk, rst, inp, out);
+module attrib01_foo(clk, rst, inp, out);
input wire clk;
input wire rst;
input wire inp;
output wire out;
- bar bar_instance (clk, rst, inp, out);
+ attrib01_bar bar_instance (clk, rst, inp, out);
endmodule