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| author | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-11 23:33:31 +0200 |
|---|---|---|
| committer | Ruben Undheim <ruben.undheim@gmail.com> | 2018-10-12 21:11:36 +0200 |
| commit | 75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1 (patch) | |
| tree | e8d3be5d6134dbf4fc26b47f9481f80a4bdfc4c7 /tests/simple/always02.v | |
| parent | 9850de405a11fe93e4562c86be0a0830b83c2785 (diff) | |
| download | yosys-75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1.tar.gz yosys-75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1.tar.bz2 yosys-75009ada3c2a4bcd38c52c8fb871c9e8c1f2e6b1.zip | |
Synthesis support for SystemVerilog interfaces
This time doing the changes mostly in AST before RTLIL generation
Diffstat (limited to 'tests/simple/always02.v')
0 files changed, 0 insertions, 0 deletions