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| author | Miodrag Milanović <mmicko@gmail.com> | 2022-03-17 17:15:36 +0100 |
|---|---|---|
| committer | GitHub <noreply@github.com> | 2022-03-17 17:15:36 +0100 |
| commit | 0c5279b73da7fcb4d92fc2ddd9d79a2a29254096 (patch) | |
| tree | b3961d2ea83b0bacfae2c97b3528120fa8ae606d /tests/sim | |
| parent | e1d4863a19150d6e50b3c4d6725a7f867c68d46a (diff) | |
| parent | 1f3423cd7d72d764217378200d7d1bd5ab721112 (diff) | |
| download | yosys-0c5279b73da7fcb4d92fc2ddd9d79a2a29254096.tar.gz yosys-0c5279b73da7fcb4d92fc2ddd9d79a2a29254096.tar.bz2 yosys-0c5279b73da7fcb4d92fc2ddd9d79a2a29254096.zip | |
Merge pull request #3236 from YosysHQ/micko/tb_initial
Recognize registers and set initial state for them in tb
Diffstat (limited to 'tests/sim')
0 files changed, 0 insertions, 0 deletions