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| author | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-15 09:35:53 +0100 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2022-02-16 13:27:59 +0100 |
| commit | 271ac28b417be00d7be1cc898762c8e425a0aae3 (patch) | |
| tree | fcff14974c070b2615e8eda981e5b811fc4e8905 /tests/sim/aldff.v | |
| parent | fb22d7cdc411ec52672cb7f13364651c564872db (diff) | |
| download | yosys-271ac28b417be00d7be1cc898762c8e425a0aae3.tar.gz yosys-271ac28b417be00d7be1cc898762c8e425a0aae3.tar.bz2 yosys-271ac28b417be00d7be1cc898762c8e425a0aae3.zip | |
Added test cases
Diffstat (limited to 'tests/sim/aldff.v')
| -rw-r--r-- | tests/sim/aldff.v | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/sim/aldff.v b/tests/sim/aldff.v new file mode 100644 index 000000000..eeb0f0673 --- /dev/null +++ b/tests/sim/aldff.v @@ -0,0 +1,7 @@ +module aldff( input [0:3] d, input [0:3] ad, input clk, aload, output reg [0:3] q ); + always @( posedge clk, posedge aload) + if (aload) + q <= ad; + else + q <= d; +endmodule |