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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 09:50:20 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-30 09:50:20 -0700 |
| commit | 295c18bd6b8d3fa503041904f7f7df392a4b5167 (patch) | |
| tree | 9a20c23d61a5c714ca8408c40d2e71345deff088 /tests/sat | |
| parent | 4cc74346f11e96b9a2bce1c984c674a22771a00a (diff) | |
| parent | 6919c0f9b010c94a0a1a31cd788301e78a1bcbfb (diff) | |
| download | yosys-295c18bd6b8d3fa503041904f7f7df392a4b5167.tar.gz yosys-295c18bd6b8d3fa503041904f7f7df392a4b5167.tar.bz2 yosys-295c18bd6b8d3fa503041904f7f7df392a4b5167.zip | |
Merge branch 'xc7dsp' of github.com:YosysHQ/yosys into xc7dsp
Diffstat (limited to 'tests/sat')
| -rw-r--r-- | tests/sat/initval.v | 8 |
1 files changed, 7 insertions, 1 deletions
diff --git a/tests/sat/initval.v b/tests/sat/initval.v index 5b661f8d6..81f71b5ba 100644 --- a/tests/sat/initval.v +++ b/tests/sat/initval.v @@ -1,6 +1,7 @@ -module test(input clk, input [3:0] bar, output [3:0] foo); +module test(input clk, input [3:0] bar, output [3:0] foo, asdf); reg [3:0] foo = 0; reg [3:0] last_bar = 0; + reg [3:0] asdf = 4'b1xxx; always @* foo[1:0] <= bar[1:0]; @@ -11,5 +12,10 @@ module test(input clk, input [3:0] bar, output [3:0] foo); always @(posedge clk) last_bar <= bar; + always @(posedge clk) + asdf[3] <= bar[3]; + always @* + asdf[2:0] = 3'b111; + assert property (foo == {last_bar[3:2], bar[1:0]}); endmodule |