diff options
| author | Eddie Hung <eddie@fpgeh.com> | 2019-10-08 12:41:26 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-10-08 12:41:26 -0700 |
| commit | 3fb604c75d3e8ee45d35fac8b787cb95a8adcf84 (patch) | |
| tree | f4b6d69647be12cef339bc62a98cdd8028435aae /tests/sat/initval.ys | |
| parent | ea54b5ea61ee242e1dfa7f257a10095f267b8171 (diff) | |
| download | yosys-3fb604c75d3e8ee45d35fac8b787cb95a8adcf84.tar.gz yosys-3fb604c75d3e8ee45d35fac8b787cb95a8adcf84.tar.bz2 yosys-3fb604c75d3e8ee45d35fac8b787cb95a8adcf84.zip | |
Revert "Add test that is expecting to fail"
This reverts commit c28d4b804720c2cf0086e921748219150e9631b5.
Diffstat (limited to 'tests/sat/initval.ys')
| -rw-r--r-- | tests/sat/initval.ys | 20 |
1 files changed, 0 insertions, 20 deletions
diff --git a/tests/sat/initval.ys b/tests/sat/initval.ys index 1627a37e3..2079d2f34 100644 --- a/tests/sat/initval.ys +++ b/tests/sat/initval.ys @@ -2,23 +2,3 @@ read_verilog -sv initval.v proc;; sat -seq 10 -prove-asserts - -read_verilog <<EOT -module gold(input clk, input i, output reg [1:0] o); -initial o = 2'b10; -always @(posedge clk) - o[0] <= {i,i}; -endmodule - -module gate(input clk, input i, output reg [1:0] o); -initial o = 2'b10; -always @(posedge clk) - o[0] <= i; -always @* - o[1] <= o[0]; -endmodule -EOT - -proc -miter -equiv -flatten -make_assert -make_outputs gold gate miter -sat -seq 1 -falsify -prove-asserts -show-ports miter |