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| author | Jannis Harder <me@jix.one> | 2022-12-21 14:40:58 +0100 |
|---|---|---|
| committer | Jannis Harder <me@jix.one> | 2023-01-11 18:07:16 +0100 |
| commit | f6458bab702e08ade0c15d7f7d8580cb5463d685 (patch) | |
| tree | 0cffa70adc2e04abae448b46436dea5ca982e464 /tests/sat/expose_dff.v | |
| parent | 9c6198a8272de1558d9f613d52a23c043e1c928a (diff) | |
| download | yosys-f6458bab702e08ade0c15d7f7d8580cb5463d685.tar.gz yosys-f6458bab702e08ade0c15d7f7d8580cb5463d685.tar.bz2 yosys-f6458bab702e08ade0c15d7f7d8580cb5463d685.zip | |
sim: Only check formal cells during gclk simulation updates
This is required for compatibility with non-multiclock formal semantics.
Diffstat (limited to 'tests/sat/expose_dff.v')
0 files changed, 0 insertions, 0 deletions