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authorClifford Wolf <clifford@clifford.at>2014-02-04 13:43:34 +0100
committerClifford Wolf <clifford@clifford.at>2014-02-04 13:43:34 +0100
commit7a66b38c3e7e05e712144d63691f517ecca18d1d (patch)
treeb15747a95b464ab78101d0c46caed2daaff57a00 /tests/sat/asserts.ys
parent6891fd79a32d8b528978893e88dcb8b25bf66ef0 (diff)
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Added test cases for sat command
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+read_verilog asserts.v
+hierarchy; proc; opt
+sat -verify -seq 1 -set-at 1 rst 1 -tempinduct -prove-asserts