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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-08 00:33:31 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-08-08 01:19:22 +0200 |
| commit | 98003430d672af05cff7d950e08a42526e766f74 (patch) | |
| tree | 794e254a6cc7738b224752c8235dd46d181f1577 /tests/opt | |
| parent | a24906a7d2a1e1d915235044d11db2815f0fba25 (diff) | |
| download | yosys-98003430d672af05cff7d950e08a42526e766f74.tar.gz yosys-98003430d672af05cff7d950e08a42526e766f74.tar.bz2 yosys-98003430d672af05cff7d950e08a42526e766f74.zip | |
opt_merge: Use FfInitVals.
Partial #2920 fix.
Diffstat (limited to 'tests/opt')
| -rw-r--r-- | tests/opt/bug2920.ys | 42 | ||||
| -rw-r--r-- | tests/opt/opt_merge_init.ys | 2 |
2 files changed, 43 insertions, 1 deletions
diff --git a/tests/opt/bug2920.ys b/tests/opt/bug2920.ys new file mode 100644 index 000000000..a8281a73a --- /dev/null +++ b/tests/opt/bug2920.ys @@ -0,0 +1,42 @@ +read_ilang <<EOT + +module \mod + wire input 1 \clk + attribute \init 2'00 + wire width 2 $q1 + attribute \init 2'00 + wire width 2 $q2 + wire output 2 width 4 \q + cell $dff $ff1 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 1 + connect \CLK \clk + connect \D 1'0 + connect \Q $q1 [0] + end + cell $dff $ff2 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 1 + connect \CLK \clk + connect \D 1'0 + connect \Q $q2 [0] + end + cell $dff $ff3 + parameter \CLK_POLARITY 1'1 + parameter \WIDTH 2 + connect \CLK \clk + connect \D 2'00 + connect \Q { $q1 [1] $q2 [1] } + end + connect \q [0] $q1 [0] + connect \q [1] $q2 [0] + connect \q [2] $q1 [1] + connect \q [3] $q2 [1] +end + +EOT + +opt_clean +opt_merge +opt_dff +opt_clean diff --git a/tests/opt/opt_merge_init.ys b/tests/opt/opt_merge_init.ys index 0176f09c7..20b6cabee 100644 --- a/tests/opt/opt_merge_init.ys +++ b/tests/opt/opt_merge_init.ys @@ -48,7 +48,7 @@ EOT opt_merge select -assert-count 1 t:$dff -select -assert-count 1 a:init=2'bx1 +select -assert-count 1 a:init=2'bx1 a:init=2'b1x design -reset |