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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2021-03-15 15:38:45 +0100 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2021-05-23 14:46:59 +0200 |
| commit | 1eea06bcc0750de02a460f3e949df2f68f800382 (patch) | |
| tree | 87986f2359f7ab5e63a454efe894a34e98845726 /tests/opt | |
| parent | a23d9409e7d04fcfa31a139d0cf6169be4c46fca (diff) | |
| download | yosys-1eea06bcc0750de02a460f3e949df2f68f800382.tar.gz yosys-1eea06bcc0750de02a460f3e949df2f68f800382.tar.bz2 yosys-1eea06bcc0750de02a460f3e949df2f68f800382.zip | |
Add new helper class for merging FFs into cells, use for memory_dff.
Fixes #1854.
Diffstat (limited to 'tests/opt')
| -rw-r--r-- | tests/opt/bug1854.ys | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/tests/opt/bug1854.ys b/tests/opt/bug1854.ys new file mode 100644 index 000000000..00a36ae94 --- /dev/null +++ b/tests/opt/bug1854.ys @@ -0,0 +1,17 @@ +read_verilog << EOT +module top(input clk, input [3:0] addr, output reg [0:0] dout); + reg [1:0] mem[0:15]; + initial begin + mem[0] = 2'b00; + mem[1] = 2'b01; + mem[2] = 2'b10; + mem[3] = 2'b11; + end + always @(posedge clk) + dout <= mem[addr]; +endmodule +EOT + +prep -rdff + +select -assert-none t:$dff |