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| author | Marcelina Kościelnicka <mwk@0x04.net> | 2020-08-17 17:13:17 +0200 |
|---|---|---|
| committer | Marcelina Kościelnicka <mwk@0x04.net> | 2020-08-17 17:26:36 +0200 |
| commit | 2b777bbda8ec46033244230e4e0d6bcea2822fa7 (patch) | |
| tree | 6a5c69662d04f1a8a37d0f8ea1cb5a642462e16c /tests/opt/opt_share_bug2334.ys | |
| parent | 9a4f420b4b8285bd05181b6988c35ce45e3c979a (diff) | |
| download | yosys-2b777bbda8ec46033244230e4e0d6bcea2822fa7.tar.gz yosys-2b777bbda8ec46033244230e4e0d6bcea2822fa7.tar.bz2 yosys-2b777bbda8ec46033244230e4e0d6bcea2822fa7.zip | |
opt_share: Refactor, fix some bugs.
Fixes #2334.
Fixes #2335.
Fixes #2336.
Diffstat (limited to 'tests/opt/opt_share_bug2334.ys')
| -rw-r--r-- | tests/opt/opt_share_bug2334.ys | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/opt/opt_share_bug2334.ys b/tests/opt/opt_share_bug2334.ys new file mode 100644 index 000000000..004d98349 --- /dev/null +++ b/tests/opt/opt_share_bug2334.ys @@ -0,0 +1,13 @@ +read_verilog <<EOT + +module t(input [3:0] A, input [3:0] B, input [3:0] C, input S, output [3:0] Y); + +wire [3:0] t = A + C; + +assign Y = S ? A + B : {4{t[0]}}; + +endmodule + +EOT + +equiv_opt -assert opt_share |