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author | Eddie Hung <eddie@fpgeh.com> | 2019-08-12 12:06:45 -0700 |
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committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-12 12:06:45 -0700 |
commit | 12c692f6eda7367527fde2a8aad49447a73aa643 (patch) | |
tree | 8680eefff6897b2f4b33d12b5d96a6ea8c549b5b /tests/opt/opt_rmdff.ys | |
parent | 78b30bbb1102047585d1a2eac89b1c7f5ca7344e (diff) | |
download | yosys-12c692f6eda7367527fde2a8aad49447a73aa643.tar.gz yosys-12c692f6eda7367527fde2a8aad49447a73aa643.tar.bz2 yosys-12c692f6eda7367527fde2a8aad49447a73aa643.zip |
Revert "Merge pull request #1280 from YosysHQ/revert-1266-eddie/ice40_full_adder"
This reverts commit c851dc13108021834533094a8a3236da6d9e0161, reversing
changes made to f54bf1631ff37a83733c162e6ebd188c1d5ea18f.
Diffstat (limited to 'tests/opt/opt_rmdff.ys')
-rw-r--r-- | tests/opt/opt_rmdff.ys | 26 |
1 files changed, 26 insertions, 0 deletions
diff --git a/tests/opt/opt_rmdff.ys b/tests/opt/opt_rmdff.ys new file mode 100644 index 000000000..081f81782 --- /dev/null +++ b/tests/opt/opt_rmdff.ys @@ -0,0 +1,26 @@ +read_verilog -icells opt_rmdff.v +prep +design -stash gold +read_verilog -icells opt_rmdff.v +proc +opt_rmdff + +select -assert-count 0 c:remove* +select -assert-min 7 c:keep* +select -assert-count 0 t:$dffe 7:$_DFFE_* %u c:noenable* %i + +design -stash gate + +design -import gold -as gold +design -import gate -as gate + +equiv_make gold gate equiv +hierarchy -top equiv +equiv_simple -undef +equiv_status -assert + +design -load gold +stat + +design -load gate +stat |