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| author | Clifford Wolf <clifford@clifford.at> | 2019-08-19 13:04:06 +0200 |
|---|---|---|
| committer | Clifford Wolf <clifford@clifford.at> | 2019-08-19 13:04:06 +0200 |
| commit | 1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9 (patch) | |
| tree | 7b7830c5da434964fd40792c393c45a31b8ad080 /tests/opt/opt_lut.ys | |
| parent | f20be90436b32e853d68c7e102a65d43f3843d91 (diff) | |
| parent | 3edb0abed88565447d5193f78261400655aa843a (diff) | |
| download | yosys-1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9.tar.gz yosys-1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9.tar.bz2 yosys-1e3dd0a2da1c8a6a34d2a664f938a90fc83e81a9.zip | |
Merge branch 'master' of github.com:YosysHQ/yosys into clifford/pmgen
Diffstat (limited to 'tests/opt/opt_lut.ys')
| -rw-r--r-- | tests/opt/opt_lut.ys | 4 |
1 files changed, 1 insertions, 3 deletions
diff --git a/tests/opt/opt_lut.ys b/tests/opt/opt_lut.ys index 59b12c351..a9fccbb62 100644 --- a/tests/opt/opt_lut.ys +++ b/tests/opt/opt_lut.ys @@ -1,4 +1,2 @@ read_verilog opt_lut.v -synth_ice40 -ice40_unlut -equiv_opt -map +/ice40/cells_sim.v -assert opt_lut -dlogic SB_CARRY:I0=1:I1=2:CI=3 +equiv_opt -map +/ice40/cells_sim.v -assert synth_ice40 |