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author | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
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committer | Clifford Wolf <clifford@clifford.at> | 2013-01-05 11:13:26 +0100 |
commit | 7764d0ba1dcf064ae487ee985c43083a0909e7f4 (patch) | |
tree | 18c05b8729df381af71b707748ce1d605e0df764 /tests/openmsp430/run-fm.do | |
download | yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.tar.gz yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.tar.bz2 yosys-7764d0ba1dcf064ae487ee985c43083a0909e7f4.zip |
initial import
Diffstat (limited to 'tests/openmsp430/run-fm.do')
-rw-r--r-- | tests/openmsp430/run-fm.do | 37 |
1 files changed, 37 insertions, 0 deletions
diff --git a/tests/openmsp430/run-fm.do b/tests/openmsp430/run-fm.do new file mode 100644 index 000000000..766d974c3 --- /dev/null +++ b/tests/openmsp430/run-fm.do @@ -0,0 +1,37 @@ + +set hdlin_ignore_full_case false +set hdlin_ignore_parallel_case false +set svf_ignore_unqualified_fsm_information true +set hdlin_warn_on_mismatch_message "FMR_ELAB-115 FMR_VLOG-079 FMR_VLOG-091" + +read_verilog -container r -libname WORK -01 rtl/omsp_alu.v +read_verilog -container r -libname WORK -01 rtl/omsp_and_gate.v +read_verilog -container r -libname WORK -01 rtl/omsp_clock_gate.v +read_verilog -container r -libname WORK -01 rtl/omsp_clock_module.v +read_verilog -container r -libname WORK -01 rtl/omsp_clock_mux.v +read_verilog -container r -libname WORK -01 rtl/omsp_dbg_hwbrk.v +read_verilog -container r -libname WORK -01 rtl/omsp_dbg_uart.v +read_verilog -container r -libname WORK -01 rtl/omsp_dbg.v +read_verilog -container r -libname WORK -01 rtl/omsp_execution_unit.v +read_verilog -container r -libname WORK -01 rtl/omsp_frontend.v +read_verilog -container r -libname WORK -01 rtl/omsp_mem_backbone.v +read_verilog -container r -libname WORK -01 rtl/omsp_multiplier.v +read_verilog -container r -libname WORK -01 rtl/omsp_register_file.v +read_verilog -container r -libname WORK -01 rtl/omsp_scan_mux.v +read_verilog -container r -libname WORK -01 rtl/omsp_sfr.v +read_verilog -container r -libname WORK -01 rtl/omsp_sync_cell.v +read_verilog -container r -libname WORK -01 rtl/omsp_sync_reset.v +read_verilog -container r -libname WORK -01 rtl/omsp_wakeup_cell.v +read_verilog -container r -libname WORK -01 rtl/omsp_watchdog.v +read_verilog -container r -libname WORK -01 rtl/openMSP430.v +set_top r:/WORK/openMSP430 + +read_verilog -container i -libname WORK -01 synth.v +read_verilog -container i -technology_library -libname TECH_WORK -01 ../../techlibs/stdcells_sim.v +read_verilog -container i -technology_library -libname TECH_WORK -01 sim_mul.v +set_top i:/WORK/openMSP430 + +source fsm_info.txt + +if ![verify] start_gui exit + |