Fix a regression from #3035.

1 files changed, 21 insertions, 0 deletions

diff --git a/tests/memories/trans_addr_enable.v b/tests/memories/trans_addr_enable.v
new file mode 100644
index 000000000..f366f41ad
--- /dev/null
+++ b/tests/memories/trans_addr_enable.v
@@ -0,0 +1,21 @@
+// expect-wr-ports 1
+// expect-rd-ports 1
+// expect-rd-clk \clk
+
+module top(input clk, we, rae, input [7:0] addr, wd, output [7:0] rd);
+
+reg [7:0] mem[0:255];
+
+reg [7:0] rra;
+
+always @(posedge clk) begin
+	if (we)
+		mem[addr] <= wd;
+
+	if (rae)
+		rra <= addr;
+end
+
+assign rd = mem[rra];
+
+endmodule