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| author | tux3 <barrdetwix@gmail.com> | 2019-06-05 00:47:54 +0200 |
|---|---|---|
| committer | tux3 <barrdetwix@gmail.com> | 2019-06-06 18:07:49 +0200 |
| commit | 88f59770932720cfc1e987c98e53faedd7388ed8 (patch) | |
| tree | 57bdf2f9ede3a9692449e6d83992ecba0535fcda /tests/lut/map_xor.v | |
| parent | 1332051f331108e73ac468f226034720bd856281 (diff) | |
| download | yosys-88f59770932720cfc1e987c98e53faedd7388ed8.tar.gz yosys-88f59770932720cfc1e987c98e53faedd7388ed8.tar.bz2 yosys-88f59770932720cfc1e987c98e53faedd7388ed8.zip | |
SystemVerilog support for implicit named port connections
This is the `foo foo(.port1, .port2);` SystemVerilog syntax
introduced in IEEE1800-2005.
Diffstat (limited to 'tests/lut/map_xor.v')
0 files changed, 0 insertions, 0 deletions