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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-20 07:50:05 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-20 07:50:05 +0300 |
| commit | 153ec0541c17ee8fad093c002a2724bc33dfe4b9 (patch) | |
| tree | 4fbaeb917bb00b1ef6560770e6d2164e6e7229a8 /tests/ice40/tribuf.ys | |
| parent | 749ff864aa708cb069fc5c356e5db69664fdd93e (diff) | |
| download | yosys-153ec0541c17ee8fad093c002a2724bc33dfe4b9.tar.gz yosys-153ec0541c17ee8fad093c002a2724bc33dfe4b9.tar.bz2 yosys-153ec0541c17ee8fad093c002a2724bc33dfe4b9.zip | |
Add new tests for ice40 architecture
Diffstat (limited to 'tests/ice40/tribuf.ys')
| -rw-r--r-- | tests/ice40/tribuf.ys | 6 |
1 files changed, 6 insertions, 0 deletions
diff --git a/tests/ice40/tribuf.ys b/tests/ice40/tribuf.ys new file mode 100644 index 000000000..40ded734d --- /dev/null +++ b/tests/ice40/tribuf.ys @@ -0,0 +1,6 @@ +equiv_opt -map ../../techlibs/ice40/cells_sim.v synth_ice40 +synth_ice40 +select -assert-count 1 t:SB_LUT4 +select -assert-count 1 t:SB_CARRY +select -assert-count 1 t:$_TBUF_ +write_verilog ./temp/tribuf_synth.v |