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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-30 09:45:33 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-30 09:45:33 +0300 |
| commit | d144748401df3f6d527771e6d30cc1eb1e08734e (patch) | |
| tree | 9a5b4c5701698722b3bbab0b821ec12299436358 /tests/ice40/logic.ys | |
| parent | eb0a5b2293d005d3a6a2d680b40f1449a489204d (diff) | |
| download | yosys-d144748401df3f6d527771e6d30cc1eb1e08734e.tar.gz yosys-d144748401df3f6d527771e6d30cc1eb1e08734e.tar.bz2 yosys-d144748401df3f6d527771e6d30cc1eb1e08734e.zip | |
Add new tests.
Diffstat (limited to 'tests/ice40/logic.ys')
| -rw-r--r-- | tests/ice40/logic.ys | 7 |
1 files changed, 7 insertions, 0 deletions
diff --git a/tests/ice40/logic.ys b/tests/ice40/logic.ys new file mode 100644 index 000000000..fc5e5b1d8 --- /dev/null +++ b/tests/ice40/logic.ys @@ -0,0 +1,7 @@ +read_verilog logic.v +hierarchy -top top +equiv_opt -assert -map +/ice40/cells_sim.v synth_ice40 # equivalency check +design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) +cd top # Constrain all select calls below inside the top module +select -assert-count 9 t:SB_LUT4 +select -assert-none t:SB_LUT4 %% t:* %D |