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author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-20 15:52:25 +0300 |
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committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-20 15:52:25 +0300 |
commit | 71dd412ac55860cbf51d91d26088515978f70116 (patch) | |
tree | c13ac7fde357fd1a4c0ff485a3c66bcdc40bfdca /tests/ice40/latches.v | |
parent | 153ec0541c17ee8fad093c002a2724bc33dfe4b9 (diff) | |
download | yosys-71dd412ac55860cbf51d91d26088515978f70116.tar.gz yosys-71dd412ac55860cbf51d91d26088515978f70116.tar.bz2 yosys-71dd412ac55860cbf51d91d26088515978f70116.zip |
Fix tests; Remove simulation;
- Add -map and -assert options for equiv_opt;
!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
- dffs;
- div_mod;
- latches;
- mul_pow;
- Add design -load;
- Remove simulations;
Diffstat (limited to 'tests/ice40/latches.v')
-rw-r--r-- | tests/ice40/latches.v | 58 |
1 files changed, 58 insertions, 0 deletions
diff --git a/tests/ice40/latches.v b/tests/ice40/latches.v new file mode 100644 index 000000000..9dc43e4c2 --- /dev/null +++ b/tests/ice40/latches.v @@ -0,0 +1,58 @@ +module latchp + ( input d, clk, en, output reg q ); + always @* + if ( en ) + q <= d; +endmodule + +module latchn + ( input d, clk, en, output reg q ); + always @* + if ( !en ) + q <= d; +endmodule + +module latchsr + ( input d, clk, en, clr, pre, output reg q ); + always @* + if ( clr ) + q <= 1'b0; + else if ( pre ) + q <= 1'b1; + else if ( en ) + q <= d; +endmodule + + +module top ( +input clk, +input clr, +input pre, +input a, +output b,b1,b2 +); + + +latchp u_latchp ( + .en (clk ), + .d (a ), + .q (b ) + ); + + +latchn u_latchn ( + .en (clk ), + .d (a ), + .q (b1 ) + ); + + +latchsr u_latchsr ( + .en (clk ), + .clr (clr), + .pre (pre), + .d (a ), + .q (b2 ) + ); + +endmodule |