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| author | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 12:30:35 -0700 |
|---|---|---|
| committer | Eddie Hung <eddie@fpgeh.com> | 2019-08-28 12:30:35 -0700 |
| commit | 87d5d9b8c80df696c836831df9d9eff6f20476fa (patch) | |
| tree | 1f422fbdb3f94a08100278299ccbc2233160b9c5 /tests/ice40/dpram.ys | |
| parent | ebd0a1875b74460da10d9b114e97c1468d8542db (diff) | |
| download | yosys-87d5d9b8c80df696c836831df9d9eff6f20476fa.tar.gz yosys-87d5d9b8c80df696c836831df9d9eff6f20476fa.tar.bz2 yosys-87d5d9b8c80df696c836831df9d9eff6f20476fa.zip | |
Use equiv for memory and dpram
Diffstat (limited to 'tests/ice40/dpram.ys')
| -rw-r--r-- | tests/ice40/dpram.ys | 5 |
1 files changed, 1 insertions, 4 deletions
diff --git a/tests/ice40/dpram.ys b/tests/ice40/dpram.ys index 77364e5ae..4f6a253ea 100644 --- a/tests/ice40/dpram.ys +++ b/tests/ice40/dpram.ys @@ -6,13 +6,10 @@ equiv_opt -run :prove -map +/ice40/cells_sim.v synth_ice40 memory opt -full -# TODO -#equiv_opt -run prove: -assert null miter -equiv -flatten -make_assert -make_outputs gold gate miter -#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter +sat -verify -prove-asserts -seq 3 -set-init-zero -show-inputs -show-outputs miter design -load postopt cd top select -assert-count 1 t:SB_RAM40_4K select -assert-none t:SB_RAM40_4K %% t:* %D -write_verilog dpram_synth.v |