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author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-20 15:52:25 +0300 |
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committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-20 15:52:25 +0300 |
commit | 71dd412ac55860cbf51d91d26088515978f70116 (patch) | |
tree | c13ac7fde357fd1a4c0ff485a3c66bcdc40bfdca /tests/ice40/div_mod.v | |
parent | 153ec0541c17ee8fad093c002a2724bc33dfe4b9 (diff) | |
download | yosys-71dd412ac55860cbf51d91d26088515978f70116.tar.gz yosys-71dd412ac55860cbf51d91d26088515978f70116.tar.bz2 yosys-71dd412ac55860cbf51d91d26088515978f70116.zip |
Fix tests; Remove simulation;
- Add -map and -assert options for equiv_opt;
!!! '-assert' option was commented for the next tests (unproven
$equiv cells was found):
- dffs;
- div_mod;
- latches;
- mul_pow;
- Add design -load;
- Remove simulations;
Diffstat (limited to 'tests/ice40/div_mod.v')
-rw-r--r-- | tests/ice40/div_mod.v | 13 |
1 files changed, 13 insertions, 0 deletions
diff --git a/tests/ice40/div_mod.v b/tests/ice40/div_mod.v new file mode 100644 index 000000000..64a36707d --- /dev/null +++ b/tests/ice40/div_mod.v @@ -0,0 +1,13 @@ +module top +( + input [3:0] x, + input [3:0] y, + + output [3:0] A, + output [3:0] B + ); + +assign A = x % y; +assign B = x / y; + +endmodule |