diff options
| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-30 09:45:33 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-30 09:45:33 +0300 |
| commit | d144748401df3f6d527771e6d30cc1eb1e08734e (patch) | |
| tree | 9a5b4c5701698722b3bbab0b821ec12299436358 /tests/ice40/counter.v | |
| parent | eb0a5b2293d005d3a6a2d680b40f1449a489204d (diff) | |
| download | yosys-d144748401df3f6d527771e6d30cc1eb1e08734e.tar.gz yosys-d144748401df3f6d527771e6d30cc1eb1e08734e.tar.bz2 yosys-d144748401df3f6d527771e6d30cc1eb1e08734e.zip | |
Add new tests.
Diffstat (limited to 'tests/ice40/counter.v')
| -rw-r--r-- | tests/ice40/counter.v | 17 |
1 files changed, 17 insertions, 0 deletions
diff --git a/tests/ice40/counter.v b/tests/ice40/counter.v new file mode 100644 index 000000000..52852f8ac --- /dev/null +++ b/tests/ice40/counter.v @@ -0,0 +1,17 @@ +module top (
+out,
+clk,
+reset
+);
+ output [7:0] out;
+ input clk, reset;
+ reg [7:0] out;
+
+ always @(posedge clk, posedge reset)
+ if (reset) begin
+ out <= 8'b0 ;
+ end else
+ out <= out + 1;
+
+
+endmodule
|