Rename the generic "Syntax error" message from the Verilog/SystemVerilog parser into unique,

meaningful info on the error.
Also add 13 compilation examples that triggers each of these messages.

1 files changed, 7 insertions, 0 deletions

diff --git a/tests/errors/syntax_err12.v b/tests/errors/syntax_err12.v
new file mode 100644
index 000000000..f9b5d5b0b
--- /dev/null
+++ b/tests/errors/syntax_err12.v
@@ -0,0 +1,7 @@
+interface iface;
+endinterface
+
+module a (
+  iface x = 1'b0
+);
+endmodule