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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 11:06:12 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 11:06:12 +0200 |
| commit | c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1 (patch) | |
| tree | 79cce7951390a0068beeab26be5d310222059c51 /tests/efinix/logic.ys | |
| parent | 3c41599ee1f62e4d77ba630fa1a245ef3fe236fa (diff) | |
| download | yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.tar.gz yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.tar.bz2 yosys-c2ec7ca7031e2e9c655723fcdb3ce3cb83cc74b1.zip | |
Moved all tests in arch sub directory
Diffstat (limited to 'tests/efinix/logic.ys')
| -rw-r--r-- | tests/efinix/logic.ys | 9 |
1 files changed, 0 insertions, 9 deletions
diff --git a/tests/efinix/logic.ys b/tests/efinix/logic.ys deleted file mode 100644 index fdedb337b..000000000 --- a/tests/efinix/logic.ys +++ /dev/null @@ -1,9 +0,0 @@ -read_verilog logic.v -hierarchy -top top -proc -equiv_opt -assert -map +/efinix/cells_sim.v synth_efinix # equivalency check -design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) -cd top # Constrain all select calls below inside the top module - -select -assert-count 9 t:EFX_LUT4 -select -assert-none t:EFX_LUT4 %% t:* %D |