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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 08:44:10 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-04 08:44:10 +0200 |
| commit | abb5a3a44df18a6ca18b6998f4c35aafc4284df8 (patch) | |
| tree | 3455c88211445a2ba6f3cf93585a1c625d68995b /tests/ecp5/macc.ys | |
| parent | 9e8175fc759478a7a496ac0d492cb4b6d0f13799 (diff) | |
| download | yosys-abb5a3a44df18a6ca18b6998f4c35aafc4284df8.tar.gz yosys-abb5a3a44df18a6ca18b6998f4c35aafc4284df8.tar.bz2 yosys-abb5a3a44df18a6ca18b6998f4c35aafc4284df8.zip | |
Check for MULT18X18D, since that is working now
Diffstat (limited to 'tests/ecp5/macc.ys')
| -rw-r--r-- | tests/ecp5/macc.ys | 12 |
1 files changed, 5 insertions, 7 deletions
diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys index bc6340509..f60281a54 100644 --- a/tests/ecp5/macc.ys +++ b/tests/ecp5/macc.ys @@ -1,15 +1,13 @@ read_verilog macc.v proc hierarchy -top top -#Failed because of 14 unproven cells. -equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check -#equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +# Blocked by issue #1358 (Missing ECP5 simulation models) +#equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check +equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check design -load postopt # load the post-opt design (otherwise equiv_opt loads the pre-opt design) cd top # Constrain all select calls below inside the top module +select -assert-count 1 t:MULT18X18D select -assert-count 4 t:CCU2C -select -assert-count 6 t:L6MUX21 -select -assert-count 49 t:LUT4 -select -assert-count 19 t:PFUMX select -assert-count 7 t:TRELLIS_FF -select -assert-none t:CCU2C t:L6MUX21 t:LUT4 t:PFUMX t:TRELLIS_FF %% t:* %D +select -assert-none t:CCU2C t:MULT18X18D t:TRELLIS_FF %% t:* %D |