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| author | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 09:04:02 +0200 |
|---|---|---|
| committer | Miodrag Milanovic <mmicko@gmail.com> | 2019-10-18 09:04:02 +0200 |
| commit | 0d60902fd97bba4f231f8f600434b8a69562ffff (patch) | |
| tree | 4aa61553937e9434b66c66ee16ad927665ace2ce /tests/ecp5/macc.ys | |
| parent | 7785f23719cdbcae6816415cf2dc124aba312c66 (diff) | |
| download | yosys-0d60902fd97bba4f231f8f600434b8a69562ffff.tar.gz yosys-0d60902fd97bba4f231f8f600434b8a69562ffff.tar.bz2 yosys-0d60902fd97bba4f231f8f600434b8a69562ffff.zip | |
hierarchy - proc reorder
Diffstat (limited to 'tests/ecp5/macc.ys')
| -rw-r--r-- | tests/ecp5/macc.ys | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/tests/ecp5/macc.ys b/tests/ecp5/macc.ys index f60281a54..1863ea4d2 100644 --- a/tests/ecp5/macc.ys +++ b/tests/ecp5/macc.ys @@ -1,6 +1,6 @@ read_verilog macc.v -proc hierarchy -top top +proc # Blocked by issue #1358 (Missing ECP5 simulation models) #equiv_opt -assert -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check equiv_opt -map +/ecp5/cells_sim.v synth_ecp5 # equivalency check |