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author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-27 18:12:18 +0300 |
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committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-27 18:12:18 +0300 |
commit | 134d3fea909bae02f4f814e3d649658502b44b73 (patch) | |
tree | 0a631ddcea2177e98b08779f4b45bf6e2ec39bd8 /tests/ecp5/macc.v | |
parent | aad9bad32604645e2d61f0858234a1838e8b88eb (diff) | |
download | yosys-134d3fea909bae02f4f814e3d649658502b44b73.tar.gz yosys-134d3fea909bae02f4f814e3d649658502b44b73.tar.bz2 yosys-134d3fea909bae02f4f814e3d649658502b44b73.zip |
Add tests for ecp5 architecture.
Diffstat (limited to 'tests/ecp5/macc.v')
-rw-r--r-- | tests/ecp5/macc.v | 22 |
1 files changed, 22 insertions, 0 deletions
diff --git a/tests/ecp5/macc.v b/tests/ecp5/macc.v new file mode 100644 index 000000000..115f8ce42 --- /dev/null +++ b/tests/ecp5/macc.v @@ -0,0 +1,22 @@ +module top(clk,a,b,c,set); +parameter A_WIDTH = 4; +parameter B_WIDTH = 3; +input set; +input clk; +input signed [(A_WIDTH - 1):0] a; +input signed [(B_WIDTH - 1):0] b; +output signed [(A_WIDTH + B_WIDTH - 1):0] c; +reg [(A_WIDTH + B_WIDTH - 1):0] reg_tmp_c; +assign c = reg_tmp_c; +always @(posedge clk) +begin +if(set) +begin +reg_tmp_c <= 0; +end +else +begin +reg_tmp_c <= a * b + c; +end +end +endmodule |