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| author | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-27 18:12:18 +0300 |
|---|---|---|
| committer | SergeyDegtyar <sndegtyar@gmail.com> | 2019-08-27 18:12:18 +0300 |
| commit | 134d3fea909bae02f4f814e3d649658502b44b73 (patch) | |
| tree | 0a631ddcea2177e98b08779f4b45bf6e2ec39bd8 /tests/ecp5/dpram.ys | |
| parent | aad9bad32604645e2d61f0858234a1838e8b88eb (diff) | |
| download | yosys-134d3fea909bae02f4f814e3d649658502b44b73.tar.gz yosys-134d3fea909bae02f4f814e3d649658502b44b73.tar.bz2 yosys-134d3fea909bae02f4f814e3d649658502b44b73.zip | |
Add tests for ecp5 architecture.
Diffstat (limited to 'tests/ecp5/dpram.ys')
| -rw-r--r-- | tests/ecp5/dpram.ys | 18 |
1 files changed, 18 insertions, 0 deletions
diff --git a/tests/ecp5/dpram.ys b/tests/ecp5/dpram.ys new file mode 100644 index 000000000..7762ce788 --- /dev/null +++ b/tests/ecp5/dpram.ys @@ -0,0 +1,18 @@ +read_verilog dpram.v +hierarchy -top top +proc +memory -nomap +equiv_opt -run :prove -map +/ecp5/cells_sim.v synth_ecp5 +memory +opt -full + +# TODO +#equiv_opt -run prove: -assert null +miter -equiv -flatten -make_assert -make_outputs gold gate miter +#sat -verify -prove-asserts -tempinduct -show-inputs -show-outputs miter + +design -load postopt +cd top +select -assert-count 1 t:DP16KD +select -assert-none t:DP16KD %% t:* %D +write_verilog dpram_synth.v |